Conventional approaches to implementing memory cells in a first-in first-out (FIFO) memory may include implementing a single sided dual port memory cell (SSDP) or a dual ended dual port memory cell (DEDP) . A SSDP may only require both a write operation and a read operation to be implemented from a single port.
FIG. 1 illustrates a SSDP 10 comprising a write wordline (WWL), a write bitline (WBL), a transmission gate (or pass gate) I2, an inverter I0, an inverter I1, a transmission gate I4, a read bitline (RBLB) , and a read wordline (RWL) . The inverter I0 and the inverter I1 generally form a storage element 11. The inverter I0 is generally sized greater than the inverter I1 in order for a single-ended write operation to occur. Specifically, when writing to the SSDP 10, the inverter I0 generally overpowers the inverter I1 to the extent that the cell gets written to, or flipped. To achieve high speed reads and writes, the SSDP 10 may require precharging of the bitlines prior to a read. Additionally, the SSDP may not provide operation over a wide variety of supply voltages. For example, the transmission gate I2, which is generally implemented as a n-channel device, may not pass a logic high (or "1") over a variety of supply voltages. If the transmission gate I2 is sized such that it passes a "1" in a 5 V operation, it generally cannot pass a "1" in a 3.3 V operation. Similarly, process techniques may be developed such that the transmission gate I2 can adequately pass a logic high in a 3.3 V operation, but generally at the expense of not being able to operate at a 5 V operation.
A dual ended dual port memory cell (DEDP) 20 is shown in FIG. 2. The DEDP may comprise a transmission gate 12, a transmission gate 14, a transmission gate 16, a transmission gate 18, an inverter 20, and an inverter 22. The inverter 20 and the inverter 22 generally form a storage element 24. A left wordline (LWL) is generally presented to the transmission gate 12 and the transmission gate 14. A right wordline (RWL) is generally presented to the gate of the transmission gates 16 and 18. The inverter 20 and the inverter 22 are sized similarly such that they use a minimum chip real estate. A left bitline (LBL) is connected to the inverter through the transmission gate 12. A left bitline bar (LBLB) is connected to the inverter 20, through the transmission gate 14. The left bitline LBL and the left bitline bar LBLB provide a differential write from the left port to the storage element 24. Since a differential write is performed in the DEDP 20, one inverter is generally not required to overpower the other inverter, which was generally required in writing to the SSDP 10. A read is generally performed by the left bitline bar LBLB and/or the left bitline LBL.
Similarly, the right bitline (RBL), is presented to the inverters 20 and 22 through the pass gate 16 and a right bitline bar RBLB is generally presented to the inverters 20 and 22 through the pass gate 18. During a differential write, a true signal is generally presented on the right bitline RBL and a complement signal generally presented on the right bitline bar RBLB. Since a differential writing to the DEDP 20 generally occurs, the overall sizing of the inverters 20 and 22 may be reduced, which may allow operation over a wide variety of supply voltages. However, the DEDP 20 consumes more chip real estate area then the SSDP 10 due to the additional pass gates (e.g., pass gate 16 and 18). When the DEDP is duplicated a number of times, which is typical in very large capacity memories, the area efficiency in implementing the chip may be reduced. Additionally, in a FIFO memory, it is only necessary to read from one port, not two ports as is possible with the DEDP 20. Not only would the design of the DEDP 20 be less efficient than the implementation of SSDP 10 in a FIFO buffer, but it would also implement functions not necessary in a FIFO buffer.
In an implementation using a 0.5 .mu.m technology, the inverter 20 may be implemented having a p-channel transistor with a 0.5 .mu.m channel width and a 0.55 .mu.m channel length and an n-channel transistor with a 1.8 .mu.m channel width and a 0.5 .mu.m channel length. The inverter 22 may have a similar channel size. If the pass gates 12, 14, 16 and 18 are implemented having a channel width of 0.5 .mu.m and a channel length of 0.55 .mu.m, the overall area consumed by the DEDP 20 may be approximately 7.7 .mu.m by 4.7 .mu.m, or 36.19 .mu.m.